Embodiments generally relate to systems, devices, and methods for circuit design. More particularly, embodiments generally relate to systems, devices, and methods for automating the debugging of design models and verification environments for simulated hardware designs as part of electronic design automation.
Modern circuit design of integrated circuits (ICs) is a combination of automated design and debug of the design. ICs are often automatically designed using specialized computer program code that serves as simulation of the IC. The design of complex ICs generally requires a high level of design verification before millions of dollars are committed to the manufacture of the ICs. Design verification typically includes running a verification program on a design, often referred to as a design under test (DUT). Much of the verification may be carried out by simulation of the DUT at a logical level, where the DUT is modeled with one or more hardware description languages (HDLs).
A verification environment (VE) may be created to simulate the DUT, check the responses from the simulated DUT, and collect coverage information used to measure the degree to which the DUT was exercised during verification. VEs are typically written in one or more verification languages, such as e, System Verilog, or SystemC.
Failures in a DUT are often encountered during simulation of the DUT by the VE. The failures typically indicate potential problems with the DUT or the VE. The output of failure information may form an important part of the verification process as the failure information may reveal design errors of the DUT and/or the VE that need to be debugged and fixed before an IC is fabricated. Each piece of failure information output from a verification process is typically examined and diagnosed in an attempt to ensure that no errors are overlooked prior to fabrication.
The process of diagnosing failures in a DUT during the verification process is typically referred to as debugging. Verification engineers typically examine raw data from a set of verification tests (often referred to as “runs”) in an attempt to locate and fix bugs in a DUT. Debugging a DUT is typically a challenging intellectual process that traditionally has been conducted by expert engineers. Continuously running simulations generates a relatively large amount of failure data to be reviewed for DUT debug by a team of design verification experts, technicians, and the like devoted to debugging. Due to the relatively large amount of data generated by running a simulation of a DUT, these engineers and technicians may spend relatively large amount of time and mental effort to analyze data to locate bugs. The debug process is a bottleneck in the design process, which affects engineering costs and schedules for moving IC to market.